Functional Description
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 2-14
ID073015 Non-Confidential
Figure 2-4 Power domains for the Cortex-A9 processor
The FPU is part of the processor power domain. The FPU clock is based on the processor clock.
There is static and dynamic high-level clock-gating. NEON SIMD data paths and logic are in a
separate power domain, with dedicated clock and reset signals. There is static and dynamic
high-level clock-gating.
When NEON is present, you can run FPU (non-SIMD) code without powering the SIMD part
or clocking the SIMD part.
Core0
NEON
SIMD
CPU0 logic + FPU +
Shared FPU/MPE logic
and register file
Clamp
Vmpe0
Vcpu0
Clamp
CPU0
RAMS
Vram0
Clamp/
Level shifter
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