Signal Descriptions
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-23
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A.13.4 Miscellaneous debug interface signals
Table A-28 shows the miscellaneous debug interface signals.
See Chapter 10 Debug.
Table A-28 Miscellaneous debug signals
Name I/O
Source or
destination
Description
COMMRX O Debug comms channel Communications channel receive.
Receive portion of Data Transfer Register full flag:
0 Empty.
1 Full.
COMMTX O Debug comms channel Communications channel transmit.
Transmit portion of Data Transfer Register full flag:
0 Empty.
1 Full.
DBGNOPWRDWN O Debugger The debugger has requested that the Cortex-A9 processor is not
powered down.
DBGSWENABLE I External debugger When LOW only the external debug agent can modify the debug
registers.
0 Not enabled.
1 Enabled.
DBGROMADDR[31:12] I System configuration Specifies bits [31:12] of the ROM table physical address.
If the address cannot be determined tie this signal LOW.
DBGROMADDRV I Valid signal for DBGROMADDR.
If the address cannot be determined tie this signal LOW.
DBGSELFADDR[31:15] I Specifies bits [31:15] of the two’s complement signed offset from the
ROM table physical address to the physical address where the debug
registers are memory-mapped.
If the offset cannot be determined tie this signal LOW.
DBGSELFADDRV I Valid signal for DBGSELFADDR.
If the offset cannot be determined tie this signal LOW.
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