ARM Cortex A9 User Manual

Signal Descriptions
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A.13.2 APB interface signals
Table A-26 shows the APB interface signals.
A.13.3 CTI signals
Table A-27 shows the CTI signals.
Table A-26 APB interface signals
Name I/O
Source or
destination
Description
PADDRDBG[12:2] I CoreSight
APB devices
Programming address.
PADDRDBG31 I APB address bus bit [31]:
0 Not an external debugger access.
1 External debugger access.
PENABLEDBG I Indicates a second and subsequent cycle of a transfer.
PSELDBG I Debug registers select:
0 Debug registers not selected.
1 Debug registers selected.
PWDATADBG[31:0] I APB write data.
PWRITEDBG I APB read/write signal.
PRDATADBG[31:0] O APB read data bus.
PREADYDBG O APB slave ready. An APB slave can assert PREADY to extend a transfer.
PSLVERRDBG O APB slave error signal.
Table A-27 CTI signals
Name I/O
Source or
destination
Description
EDBGRQ I External debugger
or CoreSight
interconnect
External debug request:
0 No external debug request.
1 External debug request.
The processor treats the EDBGRQ input as level sensitive. The EDBGRQ input
must be asserted until the processor asserts DBGACK.
DBGACK O Debug acknowledge signal.
DBGCPUDONE O Indicates that all memory accesses issued by the Cortex-A9 processor result from
operations that are performed by a debugger. active-HIGH.
DBGRESTART I Causes the processor to exit from Debug state. It must be held HIGH until
DBGRESTARTED is deasserted.
0 Not enabled.
1 Enabled.
DBGRESTARTED O Used with DBGRESTART to move between Debug state and Normal state.
0 Not enabled.
1 Enabled.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design