ARM Cortex A9 User Manual

Functional Description
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 2-11
ID073015 Non-Confidential
Entry to Dormant or Shutdown mode must be controlled through an external power controller.
Run mode
Run mode is the normal mode of operation, where all of the functionality of the Cortex-A9
processor is available.
Standby modes
WFI and WFE Standby modes disable most of the clocks in a processor, while keeping its logic
powered up. This reduces the power drawn to the static leakage current, leaving a tiny clock
power overhead requirement to enable the device to wake up.
Entry into WFI Standby mode is performed by executing the
WFI instruction.
The transition from the WFI Standby mode to the Run mode is caused by:
•An IRQ interrupt, regardless of the value of the CSPR.I bit.
•An FIQ interrupt, regardless of the value of the CSPR.F bit.
• An asynchronous abort, regardless of the value of the CPSR.A bit.
• A debug event, if invasive debug is enabled and the debug event is permitted.
• A CP15 maintenance request broadcast by other processors. This applies to the Cortex-A9
MPCore product only.
Entry into WFE Standby mode is performed by executing the
WFE instruction.
The transition from the WFE Standby mode to the Run mode is caused by:
•An IRQ interrupt, unless masked by the CPSR.I bit.
•An FIQ interrupt, unless masked by the CPSR.F bit.
• An asynchronous abort, unless masked by the CPSR.A bit.
• A debug event, if invasive debug is enabled and the debug event is permitted.
• The assertion of the EVENTI input signal.
• The execution of an
SEV instruction on any processor in the multiprocessor system. This
applies to the Cortex-A9 MPCore product only.
• A CP15 maintenance request broadcast by other processors. This applies to the Cortex-A9
MPCore product only.
The debug request can be generated by an externally generated debug request, using the
EDBGRQ pin on the Cortex-A9 processor, or from a Debug Halt instruction issued to the
Cortex-A9 processor through the APB debug port.
Standby Powered-up Powered-up Powered Up Standby modes, see Standby modes
Only wake-up logic
is clocked.
Clock is
disabled, or
powered off
Dormant Retention
state/voltage
Powered-off Powered-off External wake-up event required to wake up
Shutdown Powered-off Powered-off Powered-off External wake-up event required to wake up
Table 2-2 Cortex-A9 processor power modes (continued)
Mode
Cortex-A9
processor
RAM arrays
Cortex-A9
processor
logic
Cortex-A9
data engine
Description

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design