Revisions
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. C-7
ID073015 Non-Confidential
DSB section added About DSB on page 7-10
AXI master 0 interface attributes corrections to values Table 8-1 on page 8-2
Debug chapter moved to before PMU chapter
Figure redrawn Figure 10-2 on page 10-3
Corrections to bit format Table 10-1 on page 10-5
Footnote about CLUSTERID values added Table 4-16 on page 4-12
Value column added Table 10-10 on page 10-14
DBGCPUDONE description extended DBGCPUDONE on page 10-18
PMU management registers section added PMU management registers on page 11-5
Signal descriptions extended Configuration signals on page A-5
Signal descriptions extended, information repeated from AXI removed Table A-8 on page A-8
AWBURSTM0[1:0]
AWLENM0[3:0]
AWLOCKM0[1:0]
Signal descriptions extended, information repeated from AXI removed Table A-11 on page A-10
ARLENM0[3:0]
ARLOCKM0[1:0]
Title changed AXI Master1 signals instruction accesses on page A-11
Information repeated from AXI removed Table A-14 on page A-12
ARLENM1[3:0]
PMUEVENT[46] and PMUEVENT[47] corrected Table A-17 on page A-14
Introduction reduced, and note about
DSB
behavior added. Serializing instructions on page B-9
Table C-5 Differences between issue D and issue F (continued)
Change Location
Table C-6 Differences between issue F and issue G
Change Location Affects
Update description of transition from standby to run mode Standby modes on page 2-11 All
revisions
Addition of REVIDR
-
c15 registers on page 4-11 r3p0
Revision ID register on page 4-21 r3p0
Data cache no longer supports round robin replacement policy Table 4-35 on page 4-25
Memory system on page 7-2
From r2p0
Update description of accessing the Jazelle Configurable
Opcode Translation Table Register
Jazelle Configurable Opcode Translation Table
Register on page 5-8
All
revisions
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