To Next Page

To Previous Page

Revisions

ID073015 Non-Confidential

Clarified implementation-defined aspect of invalidating TLBs About the L1 memory system on page 7-2 All

revisions

Added information about cache policies Cortex-A9 behavior for Normal Memory Cacheable

memory regions on page 7-8

All

revisions

AWU SE RM0 [ 8: 0] encodings table corrected Table 8-5 on page 8-5 All

revisions

Update the introduction to debug register features Debug register features on page 10-4 All

revisions

Remove reference to PMU registers from Debug chapter CP14 Debug register summary on page 10-5 All

revisions

Update introduction to debug register summary Debug register summary on page 10-5 All

revisions

Remove reference to DBGDSCCR Table 10-1 on page 10-5

Debug register descriptions on page 10-7

All

revisions

Update description of BVR Table 10-5 on page 10-10 All

revisions

Move debug management registers information from debug

registers summary to debug management registers

Table 10-1 on page 10-5

Table 10-9 on page 10-13

All

revisions

Update description of debug management registers Debug management registers on page 10-13 All

revisions

Update description of DBGITCTRL and DBGDEVID registers Table 10-9 on page 10-13 All

revisions

Update description of external debug interface External debug interface on page 10-16 All

revisions

Update introduction to PMU register summary PMU register summary on page 11-3 All

revisions

Remove reference to Processor ID Registers from Debug

chapter

Table 11-1 on page 11-3 All

revisions

Update descriptions of PMICTRL and PMDEVID Table 11-2 on page 11-5 All

revisions

Update description of PMU management registers PMU management registers on page 11-5 All

revisions

Update description of performance monitoring events Performance monitoring events on page 11-7 All

revisions

Updated description of PENABLEDBG

signal Table A-26 on page A-22 All

revisions

CoreLink Level 2 Cache Controller renamed Throughout document All

revisions

Table C-6 Differences between issue F and issue G (continued)

Change Location Affects

Questions and Answers:

Need help?

Do you have a question about the ARM Cortex A9 and is the answer not in the manual?

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design