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Revisions

ID073015 Non-Confidential

Table C-7 Differences between issue G and issue H

Change Location Affects

Updated hardware configuration options for the TLB, BTAC and GHB sizes,

and the number of entries in the Instruction micro TLB.

Table 1-1 on page 1-8 r4p0

Update SCR register description c1 registers on page 4-6 All

revisions

Update PRRR and NMRR register descriptions c10 registers on page 4-10 All

revisions

Change to revision number Table 4-28 on page 4-18 r4p0

Updated TLB Type Register description TLB Type Register on page 4-19 r4p0

Updated TLB description About the MMU on page 6-2 r4p0

Main TLB on page 6-4 r4p0

Updated BTAC description About the L1 instruction side memory

system on page 7-5

r4p0

Added description of an enhanced data prefetching mechanism.

Data prefetching on page 7-11

r4p0

Updated parity error support description Parity error support on page 7-12 r4p0

Updated description of PLE Program New Channel operation PLE Program New Channel operation on

page 9-5

All

revisions

Updated heading of table describing Meaning of BVR as specified by BCR

bits [22:20]

Table 10-5 on page 10-10 All

revisions

Updated description of PMU architectural events Table 11-5 on page 11-7 All

revision

Added new PMU events Table 11-6 on page 11-8 r4p0

Updated description of WFE and WFI standby signals Table A-6 on page A-6 All

revisions

Updated description of path optimization Load and store instructions on page B-4 All

revisions

Table C-8 Differences between issue H and issue I

Change Location Affects

Revision number changes only. Main ID Register on page 4-18 r4p1

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ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design