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Level 2 Memory Interface

ID073015 Non-Confidential

Data side write bus, AWUSERM0[8:0]

Table 8-5 shows the bit encodings for AWU SE R M0 [8: 0].

8.1.5 Exclusive L2 cache

The Cortex-A9 processor can be connected to an L2 cache that supports an exclusive cache

mode. This mode must be activated both in the Cortex-A9 processor and in the L2 cache

controller.

In this mode, the data cache of the Cortex-A9 processor and the L2 cache are exclusive. At any

time, a given address is cached in either L1 data caches or in the L2 cache, but not in both. This

has the effect of greatly increasing the usable space and efficiency of an L2 cache connected to

the Cortex-A9 processor. When exclusive cache configuration is selected:

• Data cache line replacement policy is modified so that the victim line always gets evicted

to L2 memory, even if it is clean.

[5] Reserved b0

[4:1] Inner attributes

b0000

Strongly Ordered

b0001

Device

b0011

Normal Memory Non-Cacheable

b0110

Write-Through

b0111

Write-Back no Write-Allocate

b1111

Write-Back Write-Allocate.

[0] Shared bit 0 Nonshared

1 Shared.

Table 8-4 ARUSERM1[6:0] encodings (continued)

Bits Name Description

Table 8-5 AW US ERM0 [8 :0] encodings

Bits Name Description

[8] Early BRESP Enable bit Indicates that the L2 slave can send an early BRESP answer to the write request. See

Early BRESP on page 8-7.

[7] Write full line of zeros bit Indicates that the access is an entire cache line write full of zeros. See Write full line

of zeros on page 8-8.

[6] Clean eviction Indicates that the write access is the eviction of a clean cache line.

[5] L1 eviction Indicates that the write access is a cache line eviction from the L1.