ARM Cortex A9 User Manual

Debug
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-18
ID073015 Non-Confidential
3. Poll the DSCR or Authentication Status Register to check whether the processor has
already detected the changed value of these signals. This is required because the system
might not issue the signal change to the processor until several cycles after the DSB
completes.
4. Perform an
ISB , an Exception entry, or Exception exit.
The software cannot perform debug or analysis operations that depend on the new value of the
authentication signals until this procedure is complete. The same rules apply when the debugger
has control of the processor through the ITR while in debug state.
The relevant combinations of the DBGEN, NIDEN, SPIDEN, and SPNIDEN values can be
determined by polling DSCR[17:16], DSCR[15:14], or the Authentication Status Register.
10.8.4 Debug APB Interface
Use the Debug APB interface to access:
• debug registers in Table 10-1 on page 10-5
• debug management registers in Table 10-9 on page 10-13
10.8.5 External debug request interface
The following sections describe the external debug request interface signals:
• EDBGRQ
• DBGACK
• DBGCPUDONE
• COMMRX and COMMTX on page 10-19
• DBGROMADDR, and DBGSELFADDR on page 10-19.
EDBGRQ
This signal generates a halting debug event, to request the processor to enter debug state. When
this occurs, the DSCR[5:2] method of debug entry bits are set to b0100. When EDBGRQ is
asserted, it must be held until DBGACK is asserted. Failure to do so leads to
UNPREDICTABLE
behavior of the processor.
DBGACK
The processor asserts DBGACK to indicate that the system has entered debug state. It serves as
a handshake for the EDBGRQ signal. The DBGACK signal is also driven HIGH when the
debugger sets the DSCR[10] DbgAck bit to 1.
DBGCPUDONE
DBGCPUDONE is asserted when the processor has completed a DSB as part of the entry
procedure to debug state.
The processor asserts DBGCPUDONE only after it has completed all Non-debug state memory
accesses. Therefore the system can use DBGCPUDONE as an indicator that all memory
accesses issued by the processor result from operations performed by a debugger.
Figure 10-6 on page 10-19 shows the Cortex-A9 connections specific to debug request and
restart.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design