ARM Cortex A9 User Manual

Debug
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-17
ID073015 Non-Confidential
10.8.2 Authentication signals
Table 10-12 shows a list of the valid combinations of authentication signals along with their
associated debug permissions.
10.8.3 Changing the authentication signals
The NIDEN, DBGEN, SPIDEN, and SPNIDEN input signals are either tied off to some fixed
value or controlled by some external device.
If software running on the Cortex-A9 processor has control over an external device that drives
the authentication signals, it must make the change using a safe sequence:
1. Execute an implementation-specific sequence of instructions to change the signal value.
For example, this might be a single
STR instruction that writes certain value to a control
register in a system peripheral.
2. If step 1 involves any memory operation, issue a DSB.
Table 10-12 Authentication signal restrictions
SPIDEN
DBGEN
a
SPNIDEN NIDEN
Secure
b
invasive
debug
permitted
Non-secure
invasive
debug
permitted
Secure
non-invasive
debug
permitted
Non-secure
non-invasive
debug
permitted
0 0 0 0 No No No No
0 0 0 1 No No No Yes
0 0 1 0 No No No No
00 1 1NoNo Yes Yes
01 0 0NoYes No Yes
01 0 1NoYes No Yes
0 1 1 0 No Ye s Yes Ye s
0 1 1 1 No Ye s Yes Ye s
1 0 0 0 No No No No
10 0 1NoNo Yes Yes
1 0 1 0 No No No No
10 1 1NoNo Yes Yes
1 1 0 0 Yes Yes Yes Yes
1 1 0 1 Yes Yes Yes Yes
1 1 1 0 Yes Yes Yes Yes
1 1 1 1 Yes Yes Yes Yes
a. When DBGEN is LOW, the processor behaves as if DBGDSCR[15:14] equals b00 with the exception that halting debug
events are ignored when this signal is LOW.
b. Invasive debug is defined as those operations that affect the behavior of the processor. For example, taking a breakpoint is
defined as invasive debug but performance counters and trace are non-invasive.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design