ARM Cortex A9 User Manual

Signal Descriptions
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Write response channel signals
Table A-10 shows the AXI write response channel signals for AXI Master0.
Read address channel signals for AXI Master0
Table A-11 shows the AXI read address channel signals for AXI Master0.
Table A-10 Write response channel signals for AXI Master0
Name I/O Source or destination Description
BIDM0[1:0] I AXI system devices Response ID
BREADYM0 O Response ready
BRESPM0[1:0] I Write response
BVALIDM0 I Response valid
Table A-11 Read address channel signals for AXI Master0
Name I/O
Source or
destination
Description
ARADDRM0[31:0] O AXI system devices Address.
ARBURSTM0[1:0] O Burst type:
b001 INCR incrementing burst.
b010 WRAP Wrapping burst.
ARCACHEM0[3:0] O Cache type giving additional information about cacheable
characteristics.
ARIDM0[1:0] O Request ID.
ARLENM0[3:0] O The number of data transfers that can occur within each burst.
ARLOCKM0[1:0] O Lock type.
ARPROTM0[2:0] O Protection type.
ARREADYM0 I Address ready.
ARSIZEM0[1:0] O AXI system devices Burst size:
b000 8-bit transfer.
b001 16-bit transfer.
b010 32-bit transfe.r
b011 64-bit transfer.
ARUSERM0[4:0] O [4:1] memory type and Inner cache policy:
b0000 Strongly Ordered.
b0001 Device.
b0011 Normal Memory Non-Cacheable.
b0110 Write-Through.
b0111 Write-Back no Write-Allocate.
b1111 Write-Back Write-Allocate.
[0] shared.
ARVALIDM0 O Address valid.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design