ARM Cortex A9 User Manual

Signal Descriptions
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-9
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Write data channel signals
Table A-9 shows the AXI write data signals for AXI Master0.
AWLENM0[3:0] O AXI system devices The number of data transfers that can occur within each burst.
AW LO CKM 0[ 1: 0] O Lock type.
AW PR OTM 0[ 2: 0] O Protection type.
AWREADYM0 I Address ready.
AWSIZEM0[1:0] O Data transfer size:
b000 8-bit transfer.
b001 16-bit transfer.
b010 32-bit transfe.r
b011 64-bit transfer.
AWUSERM0[8:0] O [8] early BRESP. Used with L2C-310.
[7] write full line of zeros. Used with the L2C-310.
[6] clean eviction.
[5] level 1 eviction.
[4:1] memory type and Inner cache policy:
b0000 Strongly-ordered.
b0001 Device.
b0011 Normal Memory Non-Cacheable.
b0110 Write-Through.
b0111 Write-Back no Write-Allocate.
b1111 Write-Back Write-Allocate.
[0] shared.
AW VA LID M0 O Address valid.
Table A-8 Write address channel signals for AXI Master0 (continued)
Name I/O
Source or
destination
Description
Table A-9 AXI-W signals for AXI Master0
Name I/O Source or destination Description
WDATAM0[63:0] O AXI system devices Write data
WIDM0[1:0] O Write ID
WLASTM0 O Write last indication
WREADYM0 I Write ready
WSTRBM0[7:0] O Write byte lane strobe
WVALIDM0 O Write valid

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design