ARM Cortex A9 User Manual

Level 1 Memory System
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 7-7
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Return stack predictions
The return stack stores the address and the instruction execution state of the instruction after a
function-call type branch instruction. This address is equal to the link register value stored in
r14. The following instructions cause a return stack push if predicted:
•
BL immediate
•
BLX(1) immediate
•
BLX(2) register
•
HBL (ThumbEE state)
•
HBLP (ThumbEE state).
The following instructions cause a return stack pop if predicted:
•
BX r14
• MOV pc, r14
• LDM r13, {…pc}
• LDR pc, [r13] .
The
LDR instruction can use any of the addressing modes, as long as r13 is the base register.
Additionally, in ThumbEE state you can also use r9 as a stack pointer so the
LDR and LDM
instructions with pc as a destination and r9 as a base register are also treated as a return stack
pop.
Because return-from-exception instructions can change processor privilege mode and security
state, they are not predicted. This includes the
LDM(3) instruction, and the MOVS pc, r14
instruction.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design