ARM Cortex A9 User Manual

Level 1 Memory System
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 7-6
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Instruction Cache Controller
The instruction cache controller fetches the instructions from memory depending
on the program flow predicted by the prefetch unit.
The instruction cache is 4-way set associative. It comprises the following
features:
• configurable sizes of 16KB, 32KB, or 64KB
• Virtually Indexed Physically Tagged (VIPT)
• 64-bit native accesses to provide up to four instructions per cycle to the
prefetch unit
• Security Extensions support
• no lockdown support.
7.3.1 Enabling program flow prediction
You can enable program flow prediction by setting the Z bit in the CP15 c1 Control Register to
1. See System Control Register on page 4-25. Before switching program flow prediction on, you
must perform a BTAC flush operation.
This has the additional effect of setting the GHB into a known state.
7.3.2 Program flow prediction
The following sections describe program flow prediction:
• Predicted and nonpredicted instructions
• Thumb state conditional branches
• Return stack predictions on page 7-7.
Predicted and nonpredicted instructions
This section shows the instructions that the processor predicts. Unless otherwise specified, the
list applies to ARM, Thumb, ThumbEE, and Jazelle instructions.As a general rule, the flow
prediction hardware predicts all branch instructions regardless of the addressing mode,
including:
• conditional branches
• unconditional branches
• indirect branches
• PC-destination data-processing operations
• branches that switch between ARM and Thumb states.
However, some branch instructions are nonpredicted:
• Branches that switch between states (except ARM to Thumb transitions, and Thumb to
ARM transitions).
• Instructions with the S suffix are not predicted, because they are typically used to return
from exceptions and have side effects that can change privilege mode and security state.
• All mode changing instructions.
Thumb state conditional branches
In Thumb state, a branch that is normally encoded as unconditional can be made conditional by
inclusion in an If-Then-Else (ITE) block. Then it is treated as a normal conditional branch.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design