ARM Cortex A9 User Manual

Revisions
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. C-5
ID073015 Non-Confidential
Footnote e removed Table 4-3 on page 4-6
Preload Engine registers added c11 registers on page 4-10
- PLE ID Register on page 4-36
- PLE Activity Status Register on page 4-36
- PLE FIFO Status Register on page 4-37
- Preload Engine User Accessibility Register on page 4-38
- Preload Engine Parameters Control Register on
page 4-39
4.4 CP14 Jazelle registers and 4.5 CP14 Jazelle register descriptions in a
new chapter
Chapter 5 Jazelle DBX registers
Chapter 5 Memory Management Unit, 5.6 MMU software-accessible
registers section removed
-
Level 1 Memory System chapter, Cortex-A9 cache policies section
removed
-
Prefetch hint to the L2 memory interface, description rewritten and
extended
Prefetch hint to the L2 memory interface on page 8-7
Clarifications of BRESP and cache controller behavior Early BRESP on page 8-7
Write full line of zeros, signal name corrected to AWUSE RM 0[7 ] Write full line of zeros on page 8-8
Speculative coherent requests section added Speculative coherent requests on page 8-8
Removed sentence about tying unused bits of PARITYFAIL HIGH Parity error support on page 7-12
Added PE description Chapter 9 Preload Engine
Added PMU description Chapter 11 Performance Monitoring Unit
Debug chapter, About debug systems removed -
Debug chapter, Debugging modes removed -
Duplicates of ARM Architecture Reference Manual material removed -
External debug interface, description of PADDRDBG[12:0] added External debug interface on page 10-16
Debug APB interface section added Debug APB Interface on page 10-18
Amended and extended signals descriptions, source destination column
added
Appendix A Signal Descriptions
PMUEVENT[46] description corrected Table A-17 on page A-14
PMUEVENT[47] description corrected
Removed AC Characteristics Appendix -
Table C-4 Differences between issue C and issue D (continued)
Change Location

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design