ARM Cortex A9 User Manual

Revisions
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. C-4
ID073015 Non-Confidential
Table C-4 Differences between issue C and issue D
Change Location
Included Preload Engine (PE) in block diagram Figure 1-1 on page 1-2
Amended interrupt signals
Clarified data engine options Data engine on page 1-2
Clarified system design components System design components on page 1-3
Clarified Compliance Compliance on page 1-5
Added PE to features Features on page 1-6
Included PE and PE FIFO size in configurable options Configurable options on page 1-8
Clarified NEON SIMD and FPU options Table 1-1 on page 1-8
Added Test Features section Test features on page 1-9
Reworded the PTM interface section Performance monitoring on page 2-3
Added a new section for Virtualization of interrupts Virtualization of interrupts on page 2-3
Included NEON SIMD clock gating in power control description Power Control Register on page 2-9
Replaced nDERESET with nNEONRESET Reset modes on page 2-7
Added nWDRESET
Added nPERIPHRESET
Changed voltage domain boundaries and description Figure 2-4 on page 2-14
2.5.4 Date Engine logic reset replaced MPE SIMD logic reset on page 2-8
Cortex-A9 input signals DECLAMP removed, level shifters reference
removed
Communication to the power management controller on
page 2-13
Table 3-1 J and T bit encoding removed -
The Jazelle extension on page 3-3 moved The Jazelle Extension on page 3-4
NEON technology on page 3-4 renamed and rewritten Advanced SIMD architecture on page 3-5
3.4 Processor operating states removed -
3.5 Data types removed -
Multiprocessing Extensions section added Multiprocessing Extensions on page 3-7
3.6 Memory formats renamed and moved Memory model on page 3-9
3.8 Security Extensions overview renamed and moved Security Extensions architecture on page 3-6
Removed content, tables and figures from 4.1 that duplicates ARM
Architecture Reference Manual material
About system control
on page 4-2
4.2 Duplicates of ARM Architecture Reference Manual material removed,
section renamed
Register summary on page 4-3
4.3 Duplicates of ARM Architecture Reference Manual material removed,
section renamed
Register descriptions on page 4-18

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design