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Revisions

ID073015 Non-Confidential

Corrected byte address field entries. Table 10-8 on page 10-11.

Corrected interrupt signal descriptions. Table A-3 on page A-4.

Extended AXI USER descriptions. • Table A-8 on page A-8

• Table A-11 on page A-10

• Table A-14 on page A-12.

Table C-2 Differences between issue A and issue B (continued)

Change Location

Table C-3 Differences between issue B and issue C

Change Location

Removed 2.8.1 LE and BE-8 accesses on a 64-bit wide bus. -

Removed Chapter 4 Unaligned and Mixed-Endian Data Access

Support.

Removed the power management signal BISTSCLAMP.-

Added dynamic high level clock gating. Dynamic high level clock gating on page 2-9

Updated TLB information. Table 1-1 on page 1-10, Table 4-10 on page 4-15,

Table 4-37 on page 4-44

Shortened ID_MMF3[15:12] description. Memory Model Features Register 3 on page 4-49

Updated ACTLR to include reference to PL310 optimizations. Auxiliary Control Register on page 4-64

Added information about a second replacement strategy. Selection done

by SCTLR.RR bit.

System Control Register on page 4-25

Extended event information. Cortex-A9 specific events on page 4-32

Added DEFLAGS[6:0]. DEFLAGS[6:0] on page 4-37, Performance monitoring

signals on page A-14

Added Power Control Register description. Power Control Register on page 4-63

Added PL310 optimizations to L2 memory interface description. Optimized accesses to the L2 memory interface on page 8-7

Added watchpoint address masking. Watchpoint Control Registers on page 10-11

Added debug request restart diagram. Effects of resets on debug registers on page 10-4

Added CPUCLKOFF information. Table A-4 on page A-5,Unregistered signals on page B-3

Added DECLKOFF information. Table A-4 on page A-5,Unregistered signals on page B-3

Added MAXCLKLATENCY[2:0] information. Configuration signals on page A-5

Extended PMUEVENT bus description. Performance monitoring signals on page A-14

Added PMUSECURE and PMUPRIV. Performance monitoring signals on page A-14

Updated description of serializing behavior of

DMB

. Serializing instructions on page B-9

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ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design