ARM Cortex A9 User Manual

Revisions
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. C-2
ID073015 Non-Confidential
Made PMSWINC descriptions consistent. • Table 4-29 on page 4-46
• Software Increment Register on page 4-100.
Updated MIDR bits [3:0] from 0 to 1. Table 4-1 on page 4-5.
Corrected ID_MMFR3 [23:20] bit value to
0x1 . Table 4-42 on page 4-50.
Corrected AFE bit description. Table 4-51 on page 4-62.
Corrected Auxiliary Control Register bit field. • Table 4-52 on page 4-66
• Figure 4-36 on page 4-66.
Corrected S parameter values. Set/Way format on page 4-83.
Made descriptions of bits [11], [10], and [8] consistent with
table.
Figure 4-41 on page 4-87.
Corrected description of event 0x68 , architecturally
removed.
Table 4-80 on page 4-123.
Corrected TLB lockdown entries number from 8 to 4. c10, TLB Lockdown Register on page 4-134.
Corrected A, I, and F bit descriptions. c12, Interrupt Status Register on page 4-147.
Changed number of micro TLB entries from 8 to 32. Micro TLB on page 6-4.
Removed repeated information about cache types. Micro TLB on page 6-4.
Amended IRGN bits description from TTBCR to
TTBR0/TTRBR1.
Main TLB on page 6-4.
Added note about invalidating the caches and BTAC
before use.
About the L1 memory system on page 7-2.
Added parity support scheme information section. Parity error support on page 7-12.
Listed and described L2 master interfaces, M0 and M1. Cortex-A9 L2 interface on page 8-2.
Added cross reference to DBSCR external description.
Extended footnote to include reference to the DBSCR
external view.
Table 10-1 on page 10-5.
Corrected DBGDSCR description with the addition of
internal and external view descriptions.
CP14 c1, Debug Status and Control Register (DBGDSCR) on page 8-9.
Re-ordered and extended MOE bits descriptions. Table 8-2 on page 8-10.
Added more cross-references from Table 10-1. • CP14 c1, Debug Status and Control Register (DBGDSCR) on
page 8-9
• Device Power-down and Reset Status Register (DBGPRSR) on
page 8-27
• Integration Mode Control Register (DBGITCTRL) on page 8-45
• Claim Tag Clear Register (DBGCLAIMCLR) on page 8-47
• Lock Access Register (DBGLAR) on page 8-48
• Lock Status Register (DBGLSR) on page 8-49
• Authentication Status Register (DBGAUTHSTATUS) on
page 8-49
• Device Type Register (DBGDEVTYPE) on page 8-50.
Corrected Table 10-1 footnotes. Table 10-1 on page 10-5.
Table C-2 Differences between issue A and issue B (continued)
Change Location

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design