ARM Cortex A9 User Manual

Functional Description
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 2-3
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The scheme maps the 32 ARM architectural registers to a pool of 56 physical 32-bit registers,
and renames the flags (N, Z, C, V, Q, and GE) of the CPSR using a dedicated pool of eight
physical 9-bit registers.
2.1.4 PTM interface
The Cortex-A9 processor optionally implements a Program Trace Macrocell (PTM) interface,
that is compliant with the Program Flow Trace (PFT) instruction-only architecture protocol.
Waypoints, changes in the program flow or events such as changes in context ID, are output to
enable the trace to be correlated with the code image. See Program Flow Trace and Program
Trace Macrocell on page 2-4.
2.1.5 Performance monitoring
The Cortex-A9 processor provides program counters and event monitors that can be configured
to gather statistics on the operation of the processor and the memory system.
You can access performance monitoring counters and their associated control registers from the
CP15 coprocessor interface and from the APB Debug interface. See Chapter 11 Performance
Monitoring Unit.
2.1.6 Virtualization of interrupts
With virtualized interrupts a guest Operating System (OS) can use a modified version of the
exception behavior model to handle interrupts more efficiently than is possible with a software
only solution.
See Virtualization Control Register on page 4-34.
The behavior of the Virtualization Control Register depends on whether the processor is in
Secure or Non-Secure state.
If the exception occurs when the processor is in Secure state the AMO, IMO and IFO bits in the
Virtualization Control Register are ignored. Whether the exception is taken or not depends
solely on the setting of the CPSR A, I, and F bits.
If the exception occurs when the processor is in Non-secure state if the SCR EA bit, FIQ bit, or
IRQ bit is not set, whether the corresponding exception is taken or not depends solely on the
setting of the CPSR A, I, and F bits.
See Non-secure Access Control Register on page 4-32.
If the SCR.EAbit, FIQ bit or IRQ bit is set, then the corresponding exception is trapped to
Monitor mode. In this case, the corresponding exception is taken or not depending on the
CPSR.A bit, I bit, or F bits masked by the AMO, IMO, or IFO bits in the Virtualization Control
Register.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design