Jazelle DBX registers
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 5-6
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To access the JOSCR, read or write the CP14 register with:
MRC p14, 7, <Rd>, c1, c0, 0; Read JOSCR
MCR p14, 7, <Rd>, c1, c0, 0; Write JOSCR
5.3.3 Jazelle Main Configuration Register
The JMCR characteristics are:
Purpose Describes the Jazelle hardware configuration and its behavior.
Usage constraints Only accessible in privileged modes.
Configurations Available in all configurations.
Attributes See the register summary in Table 5-1 on page 5-3.
Figure 5-3 shows the JMCR bit assignments.
Figure 5-3 JMCR bit assignments
Table 5-4 shows the JMCR bit assignments.
31 30 29 28 27 26 25 10
nAR
FP
AP
OP
IS
SP
JE
UNK/SBZP
Table 5-4 JMCR bit assignments
Bits Name Function
[31] nAR not Array Operations (nAR) bit.
0 Execute array operations in hardware, if implemented. Otherwise, call the appropriate handlers in
the VM Implementation Table.
1 Execute all array operations by calling the appropriate handlers in the VM Implementation Table.
[30] FP The FP bit controls how the Jazelle hardware executes JVM floating-point opcodes:
0 Execute all JVM floating-point opcodes by calling the appropriate handlers in the VM
Implementation Table.
1 Execute JVM floating-point opcodes by issuing
VFP
instructions, where possible.
Otherwise, call the appropriate handlers in the VM Implementation Table.
In this implementation FP is set to zero and is read-only.
[29] AP The Array Pointer (AP) bit controls how the Jazelle hardware treats array references on the operand stack:
0 Array references are treated as handles.
1 Array references are treated as pointers.
[28] OP The Object Pointer (OP) bit controls how the Jazelle hardware treats object references on the operand stack:
0 Object references are treated as handles.
1 Object references are treated as pointers.
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