ARM Cortex A9 User Manual

Jazelle DBX registers
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Write operation of the JIDR
A write to the JIDR clears the translation table. This has the effect of making all configurable
opcodes executed in software only. See Jazelle Configurable Opcode Translation Table
Register on page 5-8.
5.3.2 Jazelle Operating System Control Register
The JOSCR characteristics are:
Purpose Enables operating systems to control access to Jazelle Extension
hardware.
Usage constraints The JOSCR is:
• only accessible in privileged modes.
• set to zero after a reset and must be written in privileged modes.
Configurations Available in all configurations.
Attributes See the register summary in Table 5-1 on page 5-3.
Figure 5-2 shows the JOSCR bit assignments.
Figure 5-2 JOSCR bit assignments
Table 5-3 shows the JOSCR bit assignments.
31 210
CV
CD
Reserved, RAZ
Table 5-3 JOSCR bit assignments
Bits Name Function
[31:2] - Reserved, RAZ.
[1] CV Configuration Valid bit.
0 = The Jazelle configuration is invalid. Any attempt to enter Jazelle state when the Jazelle hardware
is enabled:
• generates a configuration invalid Jazelle exception
• sets this bit, marking the Jazelle configuration as valid.
1 = The Jazelle configuration is valid. Entering Jazelle state succeeds when the Jazelle hardware is
enabled.
The CV bit is automatically cleared on an exception.
[0] CD Configuration Disabled bit.
0 = Jazelle configuration in User mode is enabled:
• reading the JIDR succeeds
• reading any other Jazelle configuration register generates an Undefined Instruction exception
• writing the JOSCR generates an Undefined Instruction exception
• writing any other Jazelle configuration register succeeds.
1 = Jazelle configuration from User mode is disabled:
• reading any Jazelle configuration register generates an Undefined Instruction exception
• writing any Jazelle configuration register generates an Undefined Instruction exception.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design