ARM Cortex A9 User Manual

Preload Engine
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 9-6
ID073015 Non-Confidential
Note
A newly programmed PLE entry is written to the PLE FIFO if the FIFO has available entries.
In cases of FIFO overflow, the instruction silently fails, and the FIFO Overflow event signal is
asserted. See Preload events in Table 11-6 on page 11-8. See PLE FIFO Status Register on
page 4-37.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design