ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-33
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Table 4-39 shows the NSACR bit assignments.
To access the NSACR, read or write the CP15 register with:
MRC p15, 0,<Rd>, c1, c1, 2; Read NSACR data
MCR p15, 0,<Rd>, c1, c1, 2; Write NSACR data
See the Cortex-A9 Floating-Point Unit Technical Reference Manual and Cortex-A9 NEON
Media Processing Engine Technical Reference Manual for more information.
Table 4-39 NSACR bit assignments
Bits Name Function
[31:19] - UNK/SBZP.
[18] NS_SMP Determines if the SMP bit of the Auxiliary Control Register is writable in Non-secure state:
0 A write to Auxiliary Control Register in Non-secure state takes an Undefined Instruction
exception and the SMP bit is write ignored. This is the reset value.
1 A write to Auxiliary Control Register in Non-secure state can modify the value of the SMP
bit. Other bits are write ignored.
[17] TL Determines if lockable TLB entries can be allocated in Non-secure state:
0 Lockable TLB entries cannot be allocated. This is the reset value.
1 Lockable TLB entries can be allocated.
[16] PLE Controls NS accesses to the Preload Engine resources:
0 Only Secure accesses to CP15 c11 are permitted. All Non-secure accesses to CP15 c11 are
trapped to
UNDEFINED. This is the default value.
1 Non-secure accesses to the CP15 c11 domain are permitted. That is, PLE resources are
available in the Non-secure state.
If the Preload Engine is not implemented, this bit is RAZ/WI. See Chapter 9 Preload Engine.
[15] NSASEDIS Disable Non-secure Advanced SIMD Extension functionality:
0 This bit has no effect on the ability to write CPACR.ASEDIS. This is the reset value.
1 The CPACR.ASEDIS bit, when executing in Non-secure state, has a fixed value of 1 and
writes to it are ignored.
See the Cortex-A9 Floating-Point Unit Technical Reference Manual and Cortex-A9 NEON Media
Processing Engine Technical Reference Manual for more information.
[14] NSD32DIS Disable the Non-secure use of D16-D31 of the VFP register file:
0 This bit has no effect on the ability to write CPACR. D32DIS. This is the reset value.
1 The CPACR.D32DIS bit, when executing in Non-secure state, has a fixed value of 1 and
writes to it are ignored.
See the Cortex-A9 Floating-Point Unit Technical Reference Manual and Cortex-A9 NEON Media
Processing Engine Technical Reference Manual for more information.
[13:12] - UNK/SBZP.
[11] CP11 Determines permission to access coprocessor 11 in the Non-secure state:
0 Secure access only. This is the reset value.
1 Secure or Non-secure access.
[10] CP10 Determines permission to access coprocessor 10 in the Non-secure state:
0 0 = Secure access only. This is the reset value.
1 1 = Secure or Non-secure access.
[9:0] - UNK/SBZP.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design