ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-16
ID073015 Non-Confidential
4.2.25 Security Extensions registers
Table 4-24 shows the Security Extensions registers.
4.2.26 Preload Engine registers
Table 4-25 shows the preload engine registers.
Table 4-24 Security Extensions registers
CRn Op1 CRm Op2 Name Type Reset Description
c1 0 c1 0
SCR
ab
RW 0x00000000 Secure Configuration Register
1
SDER
a
RW 0x00000000 Secure Debug Enable Register on page 4-31
2NSACR
RW
c
-
d
Non-secure Access Control Register on page 4-32
c12 0 c0 0 VBAR RW
0x00000000
e
Vector Base Address Register
1 MVBAR RW - Monitor Vector Base Address Register
c1 0 ISR RO
0x00000000 Interrupt Status Register
a. No access in Non-secure state.
b. SCR[6] is not implemented, RAZ/WI.
c. This is RW in Secure state and RO in the Non-secure state.
d.
0x00000000 if NEON present and 0x0000C000 if NEON not present.
e. Only the secure version is reset to 0. The Non-secure version must be programmed by software.
Table 4-25 Preload engine registers
CRn Op1 CRm Op2 Name Type Reset Description
11 0 c0 0 PLEIDR
RO
a
- PLE ID Register on page 4-36
2PLEASR
RO
a
- PLE Activity Status Register on page 4-36
4PLEFSR
RO
a
- PLE FIFO Status Register on page 4-37
c1 0 PLEUAR Privileged R/W
User RO
- Preload Engine User Accessibility Register on page 4-38
1 PLEPCR Privileged R/W
User RO
- Preload Engine Parameters Control Register on
page 4-39
a. RAZ if the PLE is not present.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design