ARM Cortex A9 - Page 66

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-17
ID073015 Non-Confidential
4.2.27 TLB maintenance
Table 4-25 on page 4-16 shows the TLB maintenance operations and registers.
4.2.28 Implementation defined registers
Table 4-27 shows the implementation defined registers. These registers provide test features
and any required configuration options specific to the Cortex-A9 processor.
Table 4-26 TLB maintenance
CRn Op1 CRm Op2 Name Type Reset Description
c8 0 c3 0
TLBIALLIS
a
WO - -
1
TLBIMVAIS
b
WO - -
2
TLBIASIDIS
b
WO - -
3
TLBIMVAAIS
a
WO - -
c5, c6, or c7 0
TLBIALL
a
WO - -
1
TLBIMVA
b
WO - -
2
TLBIASID
b
WO - -
3
TLBIMVAA
a
WO - -
c10 0 c0 0
TLB Lockdown Register
c
RW 0x00000000 TLB Lockdown Register on
page 4-35
c15 5 c4 2 Select Lockdown TLB Entry for read
WO
d
- TLB lockdown operations
on page 4-43
4 Select Lockdown TLB Entry for write
WO
d
-
c5 2 Main TLB VA register
RW
d
-
c6 2 Main TLB PA register
RW
d
-
c7 2 Main TLB Attribute register
RW
d
-
a. Has no effect on entries that are locked down.
b. Invalidates the locked entry when it matches.
c. No access in Non-secure state if NSCAR.TL=0 and RW if NSACR.TL=1.
d. No access in Non-secure state.
Table 4-27 Implementation defined registers
CRn Op1 CRm Op2 Name Type Reset Description
c1 0 c0 1
ACTLR
a
RW 0x00000000 Auxiliary Control Register on page 4-27
4 c0 0 Configuration Base
Address
RW
b
-
c
Configuration Base Address Register on page 4-42
a. RO in Non-secure state if NSACR[18]=0 and RW if NSACR[18]=1.
b. RO in User Secure state and in Non-Secure state.
c. In Cortex-A9 uniprocessor implementations the Configuration Base Address is set to zero.
In Cortex-A9 MPCore implementations the Configuration Base Address is reset to PERIPHBASE[31:13] so that software can determine
the location of the private memory region.