ARM Cortex A9 User Manual

Level 1 Memory System
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 7-3
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Data cache features
The data cache has the following features:
• The data cache is physically indexed and physically tagged.
• Data cache replacement policy is pseudo random.
• Both data cache read misses and write misses are non-blocking with up to four
outstanding data cache read misses and up to four outstanding data cache write misses
being supported.
Store buffer
The Cortex-A9 processor has a store buffer with four 64-bit slots with data merging capability.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design