Level 1 Memory System
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 7-3
ID073015 Non-Confidential
Data cache features
The data cache has the following features:
• The data cache is physically indexed and physically tagged.
• Data cache replacement policy is pseudo random.
• Both data cache read misses and write misses are non-blocking with up to four
outstanding data cache read misses and up to four outstanding data cache write misses
being supported.
Store buffer
The Cortex-A9 processor has a store buffer with four 64-bit slots with data merging capability.
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