ARM Cortex A9 User Manual

ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 6-1
ID073015 Non-Confidential
Chapter 6
Memory Management Unit
This chapter describes the MMU. It contains the following sections:
• About the MMU on page 6-2
• TLB Organization on page 6-4
• Memory access sequence on page 6-6
• MMU enabling or disabling on page 6-7
• External aborts on page 6-8.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design