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ID073015 Non-Confidential

Appendix B

Cycle Timings and Interlock Behavior

This chapter describes the cycle timings of integer instructions on Cortex-A9 processors. It

contains the following sections:

• About instruction cycle timing on page B-2

• Data-processing instructions on page B-3

• Load and store instructions on page B-4

• Multiplication instructions on page B-7

• Branch instructions on page B-8

• Serializing instructions on page B-9.

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ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design