ARM Cortex A9 User Manual

Preface
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. viii
ID073015 Non-Confidential
Chapter 8 Level 2 Memory Interface
Read this for a description of the Cortex-A9 level two memory interface, the AXI
interface attributes, and information about
STRT instructions.
Chapter 9 Preload Engine
Read this for a description of the Preload Engine (PLE) and its operations.
Chapter 10 Debug
Read this for a description of the Cortex-A9 support for debug.
Chapter 11 Performance Monitoring Unit
Read this for a description of the Cortex-A9 Performance Monitoring Unit
(PMU) and associated events.
Appendix A Signal Descriptions
Read this for a summary of the Cortex-A9 signals.
Appendix B Cycle Timings and Interlock Behavior
Read this for a description of the Cortex-A9 instruction cycle timing.
Appendix C Revisions
Read this for a description of technical changes between released issues of this
book.
Glossary
The ARM Glossary is a list of terms used in ARM documentation, together with definitions for
those terms. The ARM Glossary does not contain terms that are industry standard unless the
ARM meaning differs from the generally accepted meaning.
See ARM Glossary,
http://infocenter.arm.com/help/topic/com.arm.doc.aeg0014-/index.html .
Conventions
This book uses the conventions that are described in:
• Typographical conventions
• Timing diagrams on page ix
• Signals on page ix.
Typographical conventions
The typographical conventions are:
italic Introduces special terminology, denotes cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes signal
names. Also used for terms in descriptive lists, where appropriate.
monospace Denotes text that you can enter at the keyboard, such as commands, file
and program names, and source code.
monospace Denotes a permitted abbreviation for a command or option. You can enter
the underlined text instead of the full command or option name.
monospace italic Denotes arguments to monospace text where the argument is to be
replaced by a specific value.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design