ARM Cortex A9 User Manual

Signal Descriptions
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-25
ID073015 Non-Confidential
WPTPC[31:0] O PTM device Waypoint last executed address indicator.
This is the base Link Register in the case of an exception.
Equal to 0 if the waypoint is a reset exception.
WPTT32LINK O Indicates the size of the last executed address when in Thumb state:
0 16-bit instruction.
1 32-bit instruction.
WPTTAKEN O The waypoint passed its condition codes. The address is still used,
irrespective of the value of this signal.
Must be set for all waypoints except branch.
WPTTARGETJBIT O J bit for waypoint destination.
WPTTARGETPC[31:0] O Waypoint target address.
Bit [1] must be zero if the T bit is zero.
Bit [0] must be zero if the J bit is zero.
The value is zero if WPTTYPE is either prohibited or debug.
WPTTARGETTBIT O T bit for waypoint destination.
WPTTRACEPROHIBITED O PTM device Trace is prohibited for the waypoint target.
Indicates entry to prohibited region. No more waypoints are traced until
trace can resume.
This signal must be permanently asserted if NIDEN and DBGEN are both
LOW, after the in-flight waypoints have exited the processor. Either an
exception or a serial branch is required to ensure that changes to the inputs
have been sampled.
Only one WPTVALID cycle must be seen with
WPTTRACEPROHIBITED set.
Trace stops with this waypoint and the next waypoint is an Isync packet.
See the CoreSight PTM Architecture Specification for a description of the
packets used in trace.
WPTTYPE[2:0] O Waypoint type.
b000 Direct branch.
b001 Indirect branch.
b010 Exception.
b011 DMB, DSB, ISB.
b100 Debug entry.
b101 Debug exit.
b110 Invalid.
b111 Invalid.
Debug Entry must be followed by Debug Exit.
Note
Debug exit does not reflect the execution of an instruction.
Table A-29 PTM interface signals (continued)
Name I/O
Source or
destination
Description

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design