DMD1050TS Satellite Modem Board
Revision 1
Table of Contents TOC-2 MN-DMD1050TS
3.3 Monitor & Control (M&C) ...................................................................................................................... 3–9
3.3.1 Terminal Port/ES-ES Communications (J3) ........................................................................................ 3–9
3.3.2 Terminal Mode Control ........................................................................................................................ 3–9
3.3.3 Modem Terminal Mode Control........................................................................................................... 3–9
3.3.4 Modem Setup for Terminal Mode...................................................................................................... 3–10
3.3.5 Connect the Terminal ........................................................................................................................ 3–10
3.3.6 Terminal Screens .............................................................................................................................. 3–10
3.4 Modem Remote Communications (Radyne Link Level Protocol) .................................................. 3–11
3.4.1 RLLP Protocol Structure ................................................................................................................... 3–11
3.5 Modem Setup for Ethernet M&C (J11) .............................................................................................. 3–11
3.6 M&C Default/Reset Plug Settings (JP1 & JP2) ................................................................................. 3–11
3.7 Ethernet Data Interface – (J10) .......................................................................................................... 3–12
3.8 Internal Clock....................................................................................................................................... 3–17
3.9 Loopback Features (Terrestrial & IF) ................................................................................................ 3–17
3.10 DMD1050TS Clocking Options ........................................................................................................... 3–20
3.10.1 Tx Clock Options ............................................................................................................................... 3–20
3.10.2 Rx Buffer Clock Options .................................................................................................................... 3–21
3.11 Ethernet Data Interface ....................................................................................................................... 3–22
3.12 Reed-Solomon (R-S) Codec ............................................................................................................... 3–23
3.12.1 R-S Operation in the DMD1050TS ................................................................................................... 3–23
3.12.2 R-S Code Rate .................................................................................................................................. 3–23
3.12.3 Interleaving ........................................................................................................................................ 3–23
3.13 DMD1050TS Automatic Uplink Power Control (AUPC) Operation ................................................. 3–25
3.13.1 Radyne AUPC ................................................................................................................................... 3–25
3.13.2 EF AUPC ........................................................................................................................................... 3–26
3.13.3 Near Side AUPC ............................................................................................................................... 3–26
3.14 Asynchronous Overhead Operation (J3) .......................................................................................... 3–29
3.15 Standard IBS ES-to-ES Mode ............................................................................................................. 3–31
3.16 Enhanced Asynchronous Mode (Proprietary) .................................................................................. 3–31
3.17 Satellite Control Channel (SCC) – J3 ................................................................................................ 3–32
3.17.1 SCC Framing Structure ..................................................................................................................... 3–32
3.17.2 Aggregate Data Rate ........................................................................................................................ 3–33
3.17.3 Overhead Rate Comparison ............................................................................................................. 3–34
3.17.4 Actual Overhead Rate Calculation .................................................................................................... 3–34
3.17.5 SCC Overhead Channel Setup ......................................................................................................... 3–35
3.18 EBEM Framing Unit ............................................................................................................................. 3–37
3.18.1 EBEM Mode Set Up on the DMD1050TS ......................................................................................... 3–37
3.18.2 DMD1050TS Information Throughput Adpatation (ITA) ................................................................... 3–37
3.18.3 Embedded Channel .......................................................................................................................... 3–37
3.19 STANAG Turbo Coding ...................................................................................................................... 3–38
3.20 FIPS TRANSEC Module ...................................................................................................................... 3–39
3.20.1 Traffic Encryption and Decryption Keys and Key Generation ........................................................... 3–39
3.21 DMD1050TS ID Codes (Feature Upgrades) ....................................................................................... 3–43
3.22 Strap Codes ......................................................................................................................................... 3–43
CHAPTER 4. REAR PANEL INTERFACE......................................................................... 4–1
4.1 DMD1050TS Connections ..................................................................................................................... 4–1
4.2 Compact Flash (J6) ............................................................................................................................... 4–5
4.3 Power Input (J16) .................................................................................................................................. 4–5