N9030B PXA Signal Analyzer Service Guide 253
LO Synthesizer/Reference Troubleshooting
A14 LO Synthesizer Theory of Operation
Brief Description of the Major Blocks:
—The Field Programmable Gate Array (FPGA) L.O. Controller has the
capability to pretune the A20 YTO, detect unlocks, and control the
fractional-N divider, main loop, and offset loop.
— The Main Loop contains the fractional-N divider, phase/frequency detector,
loop integrator, YTO Main and FM Coil drivers, the main loop mixer, and
switches for selecting either single-loop or dual-loop operation. The input
to the fractional-N divider is either the 4800 MHz reference (dual-loop) or
the 1st LO signal divided by 2 (single-loop). The input to the phase
frequency detector is either the 100 MHz reference divided by 2
(single-loop) or the IF of the main loop mixer (dual-loop).
— The Offset Loop is a very-low phase noise phase locked loop with coarse
frequency settability. It is only used in dual-loop operation. Its output
frequency is set to be typically 30 to 53 MHz above the desired 1st LO
frequency, but the difference will sometimes be 78 to 88 MHz to avoid
causing spurs The output of the offset loop is applied to the LO input of the
main loop mixer, where it is mixed with the output of the A20 YTO.
— The reference frequency distribution consists of power splitters for each of
the two reference signals (4800 MHz and 100 MHz) and a programmable
divider for one splitter output of the 100 MHz reference signal. The
programmable divider can be set to 2 to generate a 50 MHz reference for
use in single-loop operation or to 3 or 6 to generate a 16.6 or 33.3 MHz
reference for dual-loop operation.
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