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5 Understanding Programming
CJ2 CPU Unit Software User’s Manual
5-2 Tasks
5
5-2-4 Designing Tasks
Ensuring Data Concurrency between Cyclic and Interrupt Tasks
Data may not be concurrent if a cyclic task and an interrupt task are reading and writing the same
I/O memory addresses. Use the following procedure to disable interrupts during memory access by
cyclic task instructions.
• Immediately prior to reading or writing by a cyclic task instruction, use a DI(693) (DISABLE
INTERRUPT) instruction to disable execution of interrupt tasks.
• Use an EI(694) (ENABLE INTERRUPT) instruction immediately after processing in order to
enable interrupt task execution.
Problems may occur with data concurrency even if DI(693) and EI(694) are used to disable interrupt
tasks during execution of an instruction that requires response reception and processing (such as a
network instruction or serial communications instruction).
Additional Information
Execution of the BIT COUNTER (BCNT), BLOCK SET (BSET), and BLOCK TRANSFER
(XFER) instructions will not be interrupted for execution of interrupt task, i.e., execution of the
instruction will be completed before the interrupt task is executed, delaying the response of the
interrupt. To prevent this, separate data processing for these instructions into more than one
instructions, as shown below for XFER.
DI
EI
Cyclic task
Reading and writing I/O
memory common to
interrupt tasks.
Processing with interrupt task
execution enabled
Disabled
Enabled
Interrupt task
Interrupt task
XFER
&50
D50
D30050
XFER
&50
D0
D30000
XFER
&100
D0
D30000
XFER instruction is
not interrupted.
Processing
separated.
Interrupts are
possible as soon as
execution of XFER
has been completed.
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