12-15
12 CPU Unit Cycle Time
CJ2 CPU Unit Software User’s Manual
12-2 Computing the Cycle Time
12
12-2-8 Response Performance of Serial PLC
Links
The response times for CPU Units connected via a Serial PLC Link (polling unit to polled unit or polled
unit to polling unit) can be calculated as shown below.
These calculations assume that the peripheral service time is sufficiently long enough to handle the
required communications time.
Hardware Interrupt Response Time
Upward/downward differentiation Interrupt response time
Upward 30 µs
Downward 150 µs
Software Interrupt Response Time
Interrupt type Interrupt response time
Input interrupt in direct mode Minimum: 33 µs
Input interrupt in counter mode Minimum: 34 µs
12-2-8 Response Performance of Serial PLC Links
• Maximum I/O response time (not including hardware delay) [ms] =
Polling unit cycle time × 2 + Communications cycle time + Polled unit cycle time × 2 + Polled unit
communications time + 4 ms
• Minimum I/O response time (not including hardware delay) [ms] =
Polled unit communications time + 0.54 ms
Number of participating polled unit
nodes
The number of polled units to which links have been established within the
maximum unit number set in the polling unit.
Number of non-participating
polled unit nodes
The number of polled units not participating in the links within the maximum
unit number set in the polling unit.
Communications cycle time [ms] • With Two or More Polled Units
Polled unit communications time × Number of participating polled unit
nodes + 10 × Number of non-participating polled unit nodes
• With One Polled Unit
Polled units communications time + 10 ms
Polled unit communications time
[ms]
• Baud rate set to Standard:
Polling unit cycle time + 0.286 × [(Number of polled units + 1) × Number of
link words × 2 + 12]
• Baud rate set to Fast:
Polling unit cycle time + 0.0955 × [(Number of polled units + 1) × Number
of link words × 2 + 12]
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