Panasonic MN103S

Chapter 6
ROM Correction
VI - 10 ROM Correction Control Registers
■ ROM Correction 3 Data Register (RCR3DR: 0x7FF00138) [32-bit access register]
bp 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
Flag RC3
DT63
RC3
DT62
RC3
DT61
RC3
DT60
RC3
DT59
RC3
DT58
RC3
DT57
RC3
DT56
RC3
DT55
RC3
DT54
RC3
DT53
RC3
DT52
RC3
DT51
RC3
DT50
RC3
DT49
RC3
DT48
At reset xxxxxxxxxxxxxxxx
Access R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
bp 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Flag RC3
DT47
RC3
DT46
RC3
DT45
RC3
DT44
RC3
DT43
RC3
DT42
RC3
DT41
RC3
DT40
RC3
DT39
RC3
DT38
RC3
DT37
RC3
DT36
RC3
DT35
RC3
DT34
RC3
DT33
RC3
DT32
At reset xxxxxxxxxxxxxxxx
Access R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
bp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Flag RC3
DT31
RC3
DT30
RC3
DT29
RC3
DT28
RC3
DT27
RC3
DT26
RC3
DT25
RC3
DT24
RC3
DT23
RC3
DT22
RC3
DT21
RC3
DT20
RC3
DT19
RC3
DT18
RC3
DT17
RC3
DT16
At reset xxxxxÅxxxxxxxxxxx
Access R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
bp 1514131211109876543210
Flag RC3
DT15
RC3
DT14
RC3
DT13
RC3
DT12
RC3
DT11
RC3
DT10
RC3
DT9
RC3
DT8
RC3
DT7
RC3
DT6
RC3
DT5
RC3
DT4
RC3
DT3
RC3
DT2
RC3
DT1
RC3
DT0
At reset xxxxxxxxxxxxxxxx
Access R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
bp Flag Description Set condition
63-56
RC3DT63
to
RC3DT56
ROM correction 3 correction data Data of the address (lower 3bits set to 7) to be corrected
55-48
RC3DT55
to
RC3DT48
ROM correction 3 correction data Data of the address (lower 3bits set to 6) to be corrected
47-40
RC3DT47
to
RC3DT40
ROM correction 3 correction data Data of the address (lower 3bits set to 5) to be corrected
39-32
RC3DT39
to
RC3DT32
ROM correction 3 correction data Data of the address (lower 3bits set to 4) to be corrected
31-24
RC3DT31
to
RC3DT24
ROM correction 3 correction data Data of the address (lower 3bits set to 3) to be corrected
23-16
RC3DT23
to
RC3DT16
ROM correction 3 correction data Data of the address (lower 3bits set to 2) to be corrected
15-8
RC3DT15
to
RC3DT8
ROM correction 3 correction data Data of the address (lower 3bits set to 1) to be corrected
7-0
RC3DT7
to
RC3DT0
ROM correction 3 correction data Data of the address (lower 3bits set to 0) to be corrected