Panasonic MN103S

Chapter 6
ROM Correction
ROM Correction Control Registers VI - 9
■ ROM Correction 2 Data Register (RCR2DR: 0x7FF00128) [32-bit access register]
bp 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
Flag RC2
DT63
RC2
DT62
RC2
DT61
RC2
DT60
RC2
DT59
RC2
DT58
RC2
DT57
RC2
DT56
RC2
DT55
RC2
DT54
RC2
DT53
RC2
DT52
RC2
DT51
RC2
DT50
RC2
DT49
RC2
DT48
At reset xxxxxxxxxxxxxxxx
Access R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
bp 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Flag RC2
DT47
RC2
DT46
RC2
DT45
RC2
DT44
RC2
DT43
RC2
DT42
RC2
DT41
RC2
DT40
RC2
DT39
RC2
DT38
RC2
DT37
RC2
DT36
RC2
DT35
RC2
DT34
RC2
DT33
RC2
DT32
At reset xxxxxxxxxxxxxxxx
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Flag RC2
DT31
RC2
DT30
RC2
DT29
RC2
DT28
RC2
DT27
RC2
DT26
RC2
DT25
RC2
DT24
RC2
DT23
RC2
DT22
RC2
DT21
RC2
DT20
RC2
DT19
RC2
DT18
RC2
DT17
RC2
DT16
At reset xxxxxxxxxxxxxxxx
Access R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
bp 1514131211109876543210
Flag RC2
DT15
RC2
DT14
RC2
DT13
RC2
DT12
RC2
DT11
RC2
DT10
RC2
DT9
RC2
DT8
RC2
DT7
RC2
DT6
RC2
DT5
RC2
DT4
RC2
DT3
RC2
DT2
RC2
DT1
RC2
DT0
At reset xxxxxxxxxxxxxxxx
Access R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
bp Flag Description Set condition
63-56
RC2DT63
to
RC2DT56
ROM correction 2 correction data Data of the address (lower 3bits set to 7) to be corrected
55-48
RC2DT55
to
RC2DT48
ROM correction 2 correction data Data of the address (lower 3bits set to 6) to be corrected
47-40
RC2DT47
to
RC2DT40
ROM correction 2 correction data Data of the address (lower 3bits set to 5) to be corrected
39-32
RC2DT39
to
RC2DT32
ROM correction 2 correction data Data of the address (lower 3bits set to 4) to be corrected
31-24
RC2DT31
to
RC2DT24
ROM correction 2 correction data Data of the address (lower 3bits set to 3) to be corrected
23-16
RC2DT23
to
RC2DT16
ROM correction 2 correction data Data of the address (lower 3bits set to 2) to be corrected
15-8
RC2DT15
to
RC2DT8
ROM correction 2 correction data Data of the address (lower 3bits set to 1) to be corrected
7-0
RC2DT7
to
RC2DT0
ROM correction 2 correction data Data of the address (lower 3bits set to 0) to be corrected