Panasonic MN103S - Page 211

Chapter 8
8-bit Timer
Control Registers VIII - 21
■ Timer 3 Mode Register (TM3MD: 0x0000A185) [8-bit Access Register]
bp 76543210
Flag TM3
CNE
TM3
LDE
---TM3
CK2
TM3
CK1
TM3
CK0
At reset 00000000
Access R/W R/W R R R R/W R/W R/W
bp Flag Description Set condition
7 TM3CNE
Timer operation enable 0: Operation disabled
1: Operation enabled
6TM3LDE
Timer initialization 0: Normal operation
1: Initialization
TM3BR value is loaded into TM3BC. Timer output 3 is set to “L” level.
5-3 - - -
2-0
TM3CK2
TM3CK1
TM3CK0
Count clock source selection 000: IOCLK
001: IOCLK/8
010: IOCLK/32
011: Cascading with timer 2
100: Timer 0 underflow
101: Timer 1 underflow
110: Timer 2 underflow
111: TM3IO pin input (rising edge)
When 1/8 IOCLK and 1/32 IOCLK are used, the prescaler control reg-
ister (TM03PSC) should be set.