Panasonic MN103S - Page 210

Chapter 8
8-bit Timer
VIII - 20 Control Registers
■ Timer 2 Mode Register (TM2MD: 0x0000A184) [8-bit Access Register]
..
When the count clock source is set to IOCLK/128, set the TM2IN flag of the external prescaler control
register TMEXPSC8 to “1” and the EXPSCNE flag to “ 1”.
..
bp 76543210
Flag TM2
CNE
TM2
LDE
---TM2
CK2
TM2
CK1
TM2
CK0
At reset 00000000
Access R/W R/W R R R R/W R/W R/W
bp Flag Description Set condition
7 TM2CNE
Timer operation enable 0: Operation disabled
1: Operation enabled
6TM2LDE
Timer initialization 0: Normal operation
1: Initialization
TM2BR value is loaded into TM2BC. Timer output 2 is set to “L” level.
5-3 - - -
2-0
TM2CK2
TM2CK1
TM2CK0
Count clock source selection 000: IOCLK
001: IOCLK/8
010: IOCLK/32
011: Cascading with timer 1
100: Timer 0 underflow
101: Timer 1 underflow
110: Setting prohibited
111: TM2IO pin input (rising edge), IOCLK/128
When 1/8 IOCLK and 1/32 IOCLK are used, the prescaler control reg-
ister (TM03PSC) should be set.