Chapter 9
16-bit Timer
IX - 54 Timer Output
■ Count TIming of Timer Output
Counting up starts from matching condition of the binary counter and the compare/capture register, the output pin
is inverted to operate timer output. Table; 9.7.4 shows the preconditions for count timing of timer output and Fig-
ure; 9.7.1 shows count timing.
Table:9.7.4 Precondition for Count Timing of Timer Output
Figure:9.7.1 Count Timing of Timer Output
(A) When initialization (“1”) is written to the TMLDE flag, the binary counter is initialized to 0x0000. The pin
output (TMnOUT) is initialized to the value which is set by the timer pin polarity selection of the timer compare/
capture mode register. Reset the TMLDE flag to “0” after setting.
(B) Counting up starts from matching condition of the binary counter and the compare/capture register, the output
pin is inverted. The binary counter is initialized to 0x0000 and restarts the counting up operation.
Operation condition Setting description
TImer up/down selection Up counting
TImer compare/capture operation mode selection Compare register (single buffer)
Timer output waveform selection TImer output
Timer pin polarity selection Positive polarity output (“L” level at reset)
Timer counter clear enable Clear operation enabled
0001 0002 0000000200010000 0000 0001 0002 0000 0001 0002 0000
TMnLDE
flag
TMnCNE
flag
Outoput pin
(A)
(B)
0002
Count
clock
Compare/capture
register
Binary counter
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