Chapter 9
16-bit Timer
PWM Output IX - 59
■ Count Timing of PWM Output (1)
The polarity for output pins changes by matching of the binary counter and the compare/capture A register and
matching of the binary counter and the compare/capture B register. Table 9.8.4 shows the preconditions for PWM
output count timing, and Figure; 9.8.1 shows count timing.
Table:9.8.4 Preconditions of Count TIming of PWM Output
Figure:9.8.1 Count Timing of PWM Output (1)
Operation condition Setting description
TImer up/down selection Up counting
TImer compare/capture operation mode selection Compare register (single buffer)
Timer output waveform selection Set when TMnBC and TMnCB match
Reset when TMnBC and TMnCA match
Timer pin polarity selection Positive polarity output (TMnAEG=0)
Negative polarity output (TMnAEG=1)
Timer counter clear enable Clear operation enabled
TMnCNE
flag
Output pin
(TMnAEG=0)
Output pin
(TMnAEG=1)
M
N
0000 0001 M-1 M M+1 M+2 N-1 N 0000 0001 MM-1
Count
clock
Compare/capture B
register
Compare/capture A
register
Binary counter
Setup time for compare/capture B register
Setup time for compare/capture A register
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