Chapter 9
16-bit Timer
IX - 60 PWM Output
■ Count Timing of PWM Output (2)
The output pin polarity changes by matching of the binary counter and the compare/capture A register and the
overflow of the binary counter. Table; 9.8.5 shows the preconditions for count timing of PWM output, and Figure;
9.8.2 shows count timing.
Table:9.8.5 Preconditions of Count timing of PWM Output
Figure:9.8.2 Count TIming of PWM Output (2)
Operation condition Setting description
Timer up/down selection Up counting
Timer compare/capture operation mode selection Compare register (single buffer)
Timer output waveform selection Set when TMnBC and TMnCA match
Reset when TMnBC overflows
TImer pin polarity selection Positive polarity output (TMnAEG=0)
Negative polarity output (TMnAEG=1)
TImer counter clear enable Clear operation disabled
TMnCNE
flag
Output pin
(TMnAEG=0)
Output pin
(TMnAEG=1)
N
0000 0001 N-1 N N+1 N+2 FFFEFFFF 0000 0001 NN-1
Setup time for compare/capture A register
Overflow time of the binary counter
Count
clock
Compare/capture A
register
Binary counter
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