Chapter 10
Motor Control PWM
Operation X - 23
■ Double Buffer Load Timing
Double buffer load can be enabled by the PCRAEN flag and PCRBEN flag of the PWMMDn register. Table:
10.3.5 shows the relationship between the double buffer load timing and enable setting flag.
Table:10.3.5 Double Buffer Load Timing and Enable Setting Flag
Figure:10.3.3 Double Buffer Load TIming
■ Setting Interrupt Timing
Interrupt signal can be generated in synchronization with the PWM period. Interrupt signal generation timing is at
the PWM period underflow and overflow. Table: 10.3.6 shows the relationship between the interrupt timing and
the enable setting flag.
Table:10.3.6 Interrupt Timing and Enable Setting Flag
Load timing Flag (Register)
At PWM binary counter underflow PCRAEN(PWMMDn)
0Disabled
1 Enabled
At PWM binary counter overflow
PCRBEN(PWMMDn)
0Disabled
1 Enabled
Load timing Flag (Register)
At PWM binary counter underflow INTAEN (PWMMDn)
0Disabled
1 Enabled
At PWM binary counter overflow INTBEN (PWMMDn)
0Disabled
1 Enabled
Triangular wave(WAVEMDn=0)
Saw-tooth wave(WAVEMDn= 1)
Value to be
compared
PWM count value
Period setting
PWM count value
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