Chapter 10
Motor Control PWM
X - 24 Operation
■ Dead Time
Dead Time is designed to insert on time delay into each of the upper and lower phases when the signal is inverted
at each PWM output phase. The DTEN flag of the PWMMDn register is used to select whether to enable or dis-
able dead time. The ORMDn flag of the PWMMDn register is used to select output logic at the time of dead time
insertion. The dead time setting register (DTMSETn) is used to specify delay time inserted as dead time. Any of
“00” to “FF” can be selected as dead time with 8-bit data. The dead time counter functions in synchronization
with MCLK when the CLKSELn flag of the PWMMDn register is “1” and with IOCLK when it is “0”, and counts
by 1 every 2 clock cycles. Calculate the dead time or delay time based on “set value × 2+1”. Thus, when “00” is
specified, 1 clock cycle of dead time is inserted if dead time is enabled.
Figure:10.3.4 Dead Time
WAVEMDn = 0
Dead time insertion logic (ORMDn = 0) Dead time insertion logic (ORMDn = 1)
Period setting
Value to be
compared
Period setting
Value to be
compared
PWMxx
NPWMxx
PWMxx
NPWMxx
PWM count value
PWM basic waveform
PWM output waveform
PWM count value
PWM basic waveform
PWM output waveform
PWM count value
PWM basic waveform
PWM basic waveform
PWM output waveform
PWM output waveform
PWM count value
PWM output polarity (PXDTn, PXDTNn = 0)PWM output polarity (PXDTn, PXDTNn = 1)
Dead time insertion enable/disable (DTENn = 1: enabled/0: disabled)
Dead time count value (DTMSETn = 8 bits)
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