Chapter 13
Serial Interface 2
XIII - 14 Operation
■ Setting Edge for Output/Input
The SC2CE1 flag of the SC2CTR0 register sets the edge of transmission data output and the edge of reception
data input. Transmission data is output in synchronization with the falling edge of the clock when the SC2CE1
flag = “0” and with the rising edge of the clock when the SC2CE1=”1”. Reception data is fed in synchronization
with the rising edge of the clock when the SC2CE1 flag =”0” and with the falling edge of the clock when the
SC2CE1=”1”.
Table:13.3.2 Edge for Transmission Data Output/Reception Data Input
■ Setting Clock
A clock source is selected by the SC2PSC2 to 0 of the SC2CTR3 register and the SC2CKS1 to 0 of the SIFCLK
register. The dedicated prescaler is started to operate with selecting “prescaler operation” by the SC2PSCE flag of
the SC2CTR3 register. The SC2MST flag of the SC2CTR1 register selects an internal clock (clock master) or
external clock (clock slave). When selecting an external clock, set an internal clock whose clock cycle does not
exceed and is similar to an external clock’ by the SC2CKS register. The reason for this is that the interrupt flag
SC2TIRQ is generated by the internal clock. Table: 13.3.3 shows the internal clock source which can be set with
the SC2CKS register. Also, the internal clock can be set to 16 dividing further by the SC2CKM flag of the
SC2CTR1 register.
Table:13.3.3 Synchronous Serial Interface Internal Clock Source
..
Set the SC2SBIS and SC2SBOS flags of the SC2CTR1 register to “0” before switching clock
settings.
..
■ Setting Parity Check
No need for setting parity bit because it is not added.
SC2CE1 Edge for transmission data output Edge for reception data input
0
1
Clock source Serial 2
Internal clock
1/2 of timer underflow
1/4 of timer underflow
1/16 of timer underflow
1/64 of timer underflow
IOCLK/2
IOCLK/4
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