Chapter 13
Serial Interface 2
Operation XIII - 15
■ Last Bit of Transmission Data
Table: 13.3.4 shows the last bit data output holding period at transmission and minimum data input period of the
last bit at reception. At slave, an internal clock should be set to secure data holding time at data transmission.
Table:13.3.4 Last Bit Data Length of Data Transfer
When no start condition is specified (SC2STE flag = 0), the SBO2 output after the last bit data output holding
period can be set with the SC2FDC1-0 flags of the SC2CTR3 register as shown in Table: 13.3.5.
After reset is released, the output prior to serial transfer is “H” regardless of the setting value of the SC2FDC1-0
flags. When a start condition is specified (SC2STE), “H” is output regardless of the setting value of the SC2FDC1
to 0.
Table:13.3.5 SBO2 Output After Last Bit Data Output Holding Period (without start condition)
■ Setting Other Control Flags
The following flags need not be set or monitored because they are not used for clock synchronous communica-
tion.
Table:13.3.6 Other Control Flags
Last bit data holding period at transmission Last bit data input period at reception
At master 1-bit data length
1 bit data length (min.)
At slave
[1-bit data length of external clock × 1/2]
+[Internal clock cycle × (1/2 to 3/2)]
SC2FDC1 flag SC2FDC0 flag
SBO2 output after last bit data
output holding period
0 0 Fixed to "1"(High) output
1 0 Fixed to "0"(Low) output
X 1 Last data retained
Register Flag Description
0SC2CTR2
SC2BRKE Break status transmission control
SC2BRKF Break status reception monitor
SC2NPE Parity enable
SC2PM1 to 0 Additional bit specification
SC2FM1 to 0 Frame mode specification
SC2STR
SC2PEK Parity error detection
SC2FEF Frame error detection
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