Chapter 16
Appendix
XVI - 14 Instruction Set
XOR Dm,Dn
XOR imm16,Dn
XOR imm32,Dn
NOT Dn
BTST imm8,Dn
BTST imm16,Dn
BTST imm32,Dn2
BTST imm8,(d8,An)
BTST imm8,(abs16)
BTST imm8,(abs32)
BSET Dm,(An)
BSET imm8,(d8,An)
BSET imm8,(abs16)
BSET imm8,(abs32)
BCLR Dm,(An)
BCLR imm8,(d8,An)
BCLR imm8,(abs16)
BCLR imm8,(abs32)
Dm ^ Dn → Dn
imm16(zero_ext) ^ Dn → Dn
imm32 ^ Dn → Dn
Dn ^ 0xFFFFFFFF → Dn
imm8(zero_ext) & Dn : PSW
imm16(zero_ext) & Dn : PSW
imm32 & Dn : PSW
imm8(zero_ext) &
mem8(d8(sign_ext)+An)(zero_ext) : PSW
imm8(zero_ext) &
mem8(abs16(zero_ext))(zero_ext) : PSW
imm8(zero_ext) & mem8(abs32)(zero_ext)
: PSW
mem8(An)(zero_ext) → temp,
temp & Dm : PSW, temp | Dm → mem8(An)
mem8(d8(sign_ext) + An)(zero_ext) → temp,
temp & imm8(zero_ext): PSW,
temp | imm8(zero_ext) →
mem8(d8(sign_ext) + An)
mem8(abs16(zero_ext))(zero_ext) → temp ,
temp & imm8(zero_ext) : PSW,
temp | imm8(zero_ext) →
mem8(abs16(zero_ext))
mem8(abs32)(zero_ext) → temp ,
temp & imm8(zero_ext) : PSW,
temp | imm8(zero_ext) → mem8(abs32)
mem8(An)(zero_ext) → temp ,
temp & Dm : PSW,
temp & (Dm ^ 0xFFFFFFFF) → mem8(An)
mem(d8(sign_ext) + An)(zero_ext) → temp,
temp & imm8(zero_ext) : PSW,
temp & (imm8(zero_ext) ^ 0xFFFFFFFF) →
mem8(d8(sign_ext) + An)
mem8(abs16(zero_ext))(zero_ext) → temp ,
temp & imm8(zero_ext) : PSW,
temp & (imm8(zero_ext) ^ 0xFFFFFFFF) →
mem8(abs16(zero_ext))
mem8(abs32)(zero_ext) → temp ,
temp & imm8(zero_ext) : PSW,
temp & (imm8(zero_ext) ^ 0xFFFFFFFF) →
mem8(abs32)
Group
Mnemonic
Operation
MN1030/MN103S SERIES INSTRUCTION SET
XOR
NOT
Bit Instructions
BTST
BSET
BCLR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
z
z
z
z
z
z
z
0
0
0
0
0
0
0
0
0
0
0
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
2
4
6
2
3
4
6
4
5
7
2
4
5
7
2
4
5
7
1
1
2
1
1
1
2
4
4
5
5
5
5
6
5
5
5
6
D0
D2
D4
D0
D1
D2
D4
D2
D3
D5
D0
D2
D3
D5
D0
D2
D3
D5
1
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
2
0010
1010
1100
0010
1000
1010
1100
1010
1110
1110
0000
1010
1110
1110
0000
1010
1110
1110
3
0010
1110
1110
0011
1110
1110
1110
1111
1000
0000
1000
1111
1000
0000
1001
1111
1000
0000
4
DmDn
10Dn
10Dn
00Dn
11Dn
11Dn
11Dn
10An
0010
0010
DmAn
00An
0000
0000
DmAn
01An
0001
0001
5
<imm16
<imm32
<imm8
<imm16
<imm32
<d8
<abs16
<abs32
<d8
<abs16
<abs32
<d8
<abs16
<abs32
6
....
....
....>
....
....
....>
....
....
....>
....
....
....>
....
....
Machine Code
Flag
Code
Size
Cycle
For
-mat
7
....
....
....
....
<imm8
....
....
<imm8
....
....
<imm8
....
....
8
....>
....
....>
....
....>
....>
....
....>
....>
....
....>
....>
....
9
....
....
<imm8
....
<imm8
....
<imm8
....
10
....
....
....>
....
....>
....
....>
....
11
....
....
....
....
....
12
....>
....>
....>
....>
....>
13
<imm8
<imm8
<imm8
14
....>
....>
....>
VF
CF NF
ZF
Notes
Not used for AM30/AM31
Not used for AM30/AM31
Not used for AM30/AM31
To Next Page
Loading...
