Panasonic MN103S - Page 467

Chapter 16
Appendix
Instruction Set XVI - 15
ASR Dm,Dn ASR imm8,Dn ASR Dn LSR Dm,Dn LSR imm8,Dn LSR Dn ASL Dm,Dn ASL imm8,Dn ASL2 Dn ROR Dn ROL Dn
IF ((Dm&0x0000001F) ≠ 0) , Dn.lsb → CF,
(Dn >> (Dm & 0x0000001F))(sign_ext) → Dn
IF ((Dm&0x0000001F)=0),PC + 2 → PC IF ((imm8 & 0x1F) ≠0) , Dn.lsb → CF, (Dn >> (imm8 & 0x1F))(sign_ext) → Dn
IF ((imm8 & 0x1F)=0) , PC + 3 → PC Dn.lsb → CF, (Dn >> 1)(sign_ext) → Dn
IF ((Dm&0x0000001F) ≠ 0),Dn.lsb → CF, (Dn >> (Dm & 0x0000001F))(zero_ext) → Dn IF ((Dm&0x0000001F)=0), PC + 2 → PC IF ((imm8 & 0x1F) ≠ 0),Dn.lsb → CF, (Dn >> (imm8 & 0x1F))(zero_ext) → Dn IF ((imm8 & 0x1F)=0), PC + 3 → PC Dn.lsb → CF, (Dn >> 1)(zero_ext) → Dn IF ((Dm & 0x0000001F) ≠ 0), Dn << (Dm & 0x0000001F) → Dn IF ((Dm & 0x0000001F)=0), PC + 2 → PC IF ((imm8 & 0x1F) ≠0), Dn << (imm8 & 0x1F) → Dn
IF ((imm8 & 0x1F)=0), PC + 3 → PC (Dn << 2 ) & 0xFFFFFFFC → Dn CF << 31 → temp, Dn.lsb → CF,
(Dn >> 1)(zero_ext) | temp → Dn
CF → temp, Dn.msb → CF,
(Dn << 1) | temp → Dn
Group
Mnemonic
Operation
MN1030/MN103S SERIES INSTRUCTION SET
Shift Instructions ASR LSR ASL ASL2 ROR ROL
? ? ? ? ? ? ? ? ? ? ? ? ? 0 0
z
?
z
?
z z
?
z
?
z
? ? ?
z z
z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z
2 3 3 2 3 3 2 3 1 2 2
1 1 1 1 1 1 1 1 1 1 1
D0 D1 D0 D1 D0 D1
S0
D0 D0
1 1111 1111 1111 1111 1111 1111 0101 1111 1111
2 0010 1000 0010 1000 0010 1000 01Dn 0010 0010
3 1011 1100 1010 1100 1001 1100 1000 1000
4 DmDn 10Dn DmDn 01Dn DmDn 00Dn 01Dn 00Dn
5 <imm8 <imm8 <imm8
6 ....> ....> ....>
Machine Code
Flag
Code Size
Cycle
For -mat
789
10
11
12
13 14
VF
CF NF
ZF
Notes