Chapter 16
Appendix
XVI - 16 Instruction Set
BEQ (d8,PC)
BNE (d8,PC)
BGT (d8,PC)
BGE (d8,PC)
BLE (d8,PC)
BLT (d8,PC)
BHI (d8,PC)
BCC (d8,PC)
BLS (d8,PC)
BCS (d8,PC)
BVC (d8,PC)
BVS (d8,PC)
BNC (d8,PC)
BNS (d8,PC)
BRA (d8,PC)
LEQ
LNE
IF (ZF=1), PC + d8(sign_ext)→ PC
IF (ZF=0),PC + 2 → PC
IF (ZF=0), PC + d8(sign_ext) → PC
IF (ZF=1), PC + 2 → PC
IF ((ZF | (NF^VF))=0),PC + d8(sign_ext) → PC
IF ((ZF | (NF^VF))=1),PC + 2 → PC
IF ((NF ^ VF)=0),PC + d8(sign_ext) → PC
IF ((NF ^ VF)=1),PC + 2 → PC
IF ((ZF | (NF^VF))=1),PC + d8(sign_ext) → PC
IF ((ZF | (NF^VF))=0),PC + 2 → PC
IF ((NF ^ VF)=1),PC + d8(sign_ext) →PC
IF ((NF ^ VF)=0),PC + 2 → PC
IF ((CF | ZF)=0),PC + d8(sign_ext) → PC
IF ((CF | ZF)=1),PC + 2 →PC
IF (CF = 0),PC + d8(sign_ext) → PC
IF (CF = 1),PC + 2 → PC
IF ((CF | ZF)=1),PC + d8(sign_ext) → PC
IF ((CF | ZF)=0),PC + 2 → PC
IF (CF = 1),PC + d8(sign_ext) → PC
IF (CF = 0),PC + 2 → PC
IF (VF = 0),PC + d8(sign_ext) → PC
IF (VF = 1),PC + 3 → PC
IF (VF = 1),PC + d8(sign_ext) → PC
IF (VF = 0),PC + 3 → PC
IF (NF = 0),PC + d8(sign_ext) → PC
IF (NF = 1),PC + 3 → PC
IF (NF = 1),PC + d8(sign_ext) → PC
IF (NF = 0),PC + 3 → PC
PC + d8(sign_ext) →PC
IF (ZF=1), LAR - 4 →PC
IF (ZF=0),PC + 1 →PC
IF (ZF=0), LAR - 4 →PC
IF (ZF=1), PC + 1 →PC
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-
-
-
2
2
2
2
2
2
2
2
2
2
3
3
3
3
2
1
1
3/1*
3/1*
3/1*
3/1*
3/1*
3/1*
3/1*
3/1*
3/1*
3/1*
4/2*
4/2*
4/2*
4/2*
3
1/2*
1/2*
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
D1
D1
D1
D1
S1
S0
S0
1
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1111
1111
1111
1111
1100
1101
1101
2
1000
1001
0001
0010
0011
0000
0101
0110
0111
0100
1000
1000
1000
1000
1010
1000
1001
3
<d8
<d8
<d8
<d8
<d8
<d8
<d8
<d8
<d8
<d8
1110
1110
1110
1110
<d8
4
....>
....>
....>
....>
....>
....>
....>
....>
....>
....>
1000
1001
1010
1011
....>
5
<d8
<d8
<d8
<d8
6
....>
....>
....>
....>
Group
Mnemonic
Operation
Machine Code
Notes
Flag
Code
Size
Cycle
For
-mat
MN1030/MN103S SERIES INSTRUCTION SET
789
10
11
12
13 14
VF
CF NF
ZF
Branch Instructions
Bcc
Lcc
Branch enable/disable
Branch enable/disable
Branch enable/disable
Branch enable/disable
Branch enable/disable
Branch enable/disable
Branch enable/disable
Branch enable/disable
Branch enable/disable
Branch enable/disable
Branch enable/disable
Branch enable/disable
Branch enable/disable
Branch enable/disable
Branch enable/disable
Branch enable/disable
*:Depends on the status of Instruction queue.