Panasonic MN103S - Page 469

Chapter 16
Appendix
Instruction Set XVI - 17
LGT LGE LLE LLT LHI LCC LLS LCS LRA SETLB JMP (An) JMP label CALL label
IF ((ZF | (NF^VF))=0), LAR - 4 → PC IF ((ZF | (NF^VF))=1),PC + 1 →PC IF ((NF ^ VF)=0), LAR - 4 →PC IF ((NF ^ VF)=1),PC + 1 →PC
IF ((ZF | (NF ^ VF))=1),LAR - 4 →PC IF ((ZF | (NF ^ VF))=0),PC + 1 →PC IF ((NF ^ VF)=1),LAR - 4 →PC IF ((NF ^ VF)=0),PC + 1 →PC
IF ((CF | ZF)=0), LAR - 4 →PC
IF ((CF | ZF)=1),PC + 1 →PC
IF (CF = 0), LAR - 4 →PC IF (CF = 1),PC + 1 → PC IF ((CF | ZF)=1), LAR - 4 →PC
IF ((CF | ZF)=0),PC + 1 →PC
IF (CF = 1), LAR - 4 →PC IF (CF = 0),PC + 1 →PC LAR - 4 →PC mem32 ( PC + 1) →LIR , PC + 5 →LAR An → PC
IF (label = (d16,PC)),PC + d16(sign_ext) →PC
IF (label = (d32,PC)),PC + d32 →PC PC + 5 →mem32(SP), SP - imm8(zero_ext) →SP,PC + 5 →MDR, PC + d16(sign_ext) →PC
PC + 5 →mem32(SP),reg1 →mem32(SP-4), SP - imm8(zero_ext) →SP,PC + 5 →MDR, PC + d16(sign_ext) →PC
PC + 5 →mem32(SP),reg1→mem32(SP-4), reg2→mem32(SP),SP - imm8(zero_ext) →SP,
PC + 5 →MDR,PC + d16(sign_ext) →PC
PC + 5 →mem32(SP),reg1→mem32(SP-4), reg2→mem32(SP-8),reg3→mem32(SP), SP - imm8(zero_ext) →SP,PC + 5 →MDR, PC + d16(sign_ext) →PC
PC + 5 →mem32(SP),D2→mem32(SP-4),
D3→mem32(SP-8),A2→mem32(SP-12), A3→mem32(SP-16), SP - imm8(zero_ext) →SP,PC + 5 →MDR, PC + d16(sign_ext) →PC
- - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
1 1 1 1 1 1 1 1 1 1 2 3 5 5 5 5 5 5
1/2* 1/2* 1/2* 1/2* 1/2* 1/2* 1/2* 1/2*
1 1 3 2
3**
2 3 4 5 6
S0 S0 S0 S0 S0 S0 S0 S0 S0 S0
D0
S2 S4 S4
1 1101 1101 1101 1101 1101 1101 1101 1101 1101 1101 1111 1100 1101 1100
2 0001 0010 0011 0000 0101 0110 0111 1001 1010 1011 0000 1100 1100 1101
3 1111 <d16. <d32 <d16.
4 01An .... .... ....
5 .... .... ....
6 ....> .... ....>
Group
Mnemonic
Operation
Machine Code
Notes
Flag
Code Size
Cycle
For -mat
MN1030/MN103S SERIES INSTRUCTION SET
7 .... <regs
8 .... ....>
9 .... <imm8
10 ....> ....>
11
12
13 14
VF
CF NF
ZF
Lcc SETLB JMP CALL
Branch enable/disable Branch enable/disable Branch enable/disable Branch enable/disable Branch enable/disable Branch enable/disable Branch enable/disable Branch enable/disable **4 cycyes for AM30 If label = (d16,PC), registers specified with regs = 0 If label = (d16,PC), registers specified with regs = 1 If label = (d16,PC), registers specified with regs = 2 If label = (d16,PC), registers specified with regs = 3 If label = (d16,PC), registers specified with regs = 4
*: Depends on the status of Instruction queue.