Panasonic MN103S - Page 474

Chapter 16
Appendix
XVI - 22 Instruction Set
RETF RETS JSR (An) JSR label RTS RTI TRAP NOP
SP + imm8(zero_ext) → SP,MDR → PC, mem32(SP-4)→ reg1,mem32(SP-8)→ reg2, mem32(SP-12)→ D0,mem32(SP-16)→ D1,
mem32(SP-20)→ A0,mem32(SP-24)→ A1, mem32(SP-28)→ MDR,mem32(SP-32)→ LIR, mem32(SP-36)→ LAR SP + imm8(zero_ext) → SP,MDR → PC, mem32(SP-4)→ reg1,mem32(SP-8)→ reg2, mem32(SP-12)→ reg3,mem32(SP-16)→ D0, mem32(SP-20)→ D1,mem32(SP-24)→ A0,
mem32(SP-28)→ A1,mem32(SP-32)→ MDR, mem32(SP-36)→ LIR,mem32(SP-40)→ LAR,
SP + imm8(zero_ext) → SP,MDR → PC, mem32(SP-4)→ D2,mem32(SP-8)→ D3,
mem32(SP-12)→ A2,mem32(SP-16)→ A3, mem32(SP-20)→ D0,mem32(SP-24)→ D1,
mem32(SP-28)→ A0,mem32(SP-32)→ A1, mem32(SP-36)→ MDR,mem32(SP-40)→ LIR, mem32(SP-44)→ LAR mem32(SP) → PC SP - 4 → SP,PC + 2 → mem32(SP) PC + 2 → MDR,An → PC, (execute subroutine) SP + 4 → SP IF ( label = (d16,PC)), SP - 4 → SP,PC + 4 → mem32(SP), PC + 4 → MDR,PC + d16 (sign_ext) → PC (execute subroutine) SP+4 → SP IF ( label = (d32,PC)), SP - 4 → SP,PC + 6 → (SP+3), PC + 6 → MDR,PC + d32 → PC (execute subroutine) SP+4 → SP mem32(SP) → PC mem16(SP) → PSW,mem32(SP+4) → PC,
SP + 8 → SP PC + 2 → mem32(SP),0x40000010 → PC
PC + 1 → PC
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z z z
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z
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z z z
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z
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z z z
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z
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z z z
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z
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3 3 3 2 8
10 12
2 2 2 1
10 11 10
5*
5 5
5*
4 4 4 1
S2
D0 D0 D0
S0
1 1101 1111 1111 1111 1100
2 1110 0000 0000 0000 1011
3 <regs 1111 1111 1111
4 ....> 1100 1101 1110
5 <imm8
6 ....>
Group
Mnemonic
Operation
Machine Code
Notes
Flag
Code Size
Cycle
For -mat
MN1030/MN103S SERIES INSTRUCTION SET
789
10
11
12
13 14
VF
CF NF
ZF
RETF RETS JSR RTS RTI TRAP NOP
registers specified with regs = 9 registers specified with regs= 10 registers specified with regs= 11 *: 4 cycles for AM30 *: 6 cycles for AM30